Institutional Repository
Technical University of Crete
Technical University of Crete
EN
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| URI: | http://purl.tuc.gr/dl/dias/69B2ABAE-EA90-4347-BFDC-5352F4F01B5E | ||
| Year | 2019 | ||
| Type of Item | Master Thesis | ||
| License |
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| Bibliographic Citation | Pavlos Giakoumakis, "TensorGlue: a framework for FPGA-based deep learning design", Master Thesis, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2019 https://doi.org/10.26233/heallink.tuc.83920 | ||
| Appears in Collections |
In a deep learning framework, the designer provides a description of the neural network architecture, in the form of a computational graph (data-flow graph). The tool is able process this graph and either run it efficiently on fixed-hardware, or generate automatically additional graphs to train the neural network. Nevertheless, this kind of formalization using computational graphs is very close to the hardware design process. The graph can be processed in many ways to not only run the described architecture on fixed-hardware, but to generate hardware designs as well.In this work, we designed and implemented a novel framework that resembles deep learning frameworks but generates hardware designs in the form of synthesizable C++.
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