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Design of low power operational transconductance amplifiers(OTAs) in two generations of Bulk CMOS

Apostolakis Apostolos

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Summary

The continued need for accurate design methodologies mandates an ongoing research in this field. In this work, the Inversion Coefficient (IC) based methodology for low-power, low-voltage MOSFET design was explored. This methodology is based on design-oriented transistor parameter extraction, such as I0 (technology current), slope factor n, transconductance parameter KP etc. and several important performance metrics in the form of Figures-of-Merit (FoM), such as gm/ID and Av (intrinsic gain). To test the accuracy of this approach, two different operational transconductance amplifier (OTA) topologies were designed in low power mode of operation (power dissipation 24uW), a current mirror p- input, single-ended OTA and a p-input, fully differential, folded cascode (FDFC) OTA. To accentuate the prediction capability of this methodology, two process design kits (PDKs) were used; a 65nm bulk CMOS PDK and a 90nm bulk CMOS PDK. The structural design flow includes the procedure of parameter extraction for both PDKs, the mathematical analysis of each circuit, the design validation and optimization via simulation. All four designs were developed in Virtuoso ADE by Cadence and simulated using Spectre Simulation Platform. Open-Loop Gain (A0), Gain Bandwidth (GBW) , Phase Margin (PM), Slew Rate (SR), Input and Output Voltage ranges, Input referred Noise and Input DC offset were set as circuit performance criteria. Finally, comparative results between circuit topologies and technology nodes are presented and discussed.

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