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Mapping HPC accelerators on HARP2 platform using the DAER decoupled access-execute framework

Morianos Ioannis

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Year 2020
Type of Item Diploma Work
Bibliographic Citation Ioannis Morianos, "Mapping HPC accelerators on HARP2 platform using the DAER decoupled access-execute framework", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2020
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In the latest years, the need to process large volumes of data in a short period and the need to limit the power consumption, have shifted the computing industry vendors to build High-Performance Computing (HPC) acceleration platforms. The hybrid CPU-FPGA (Field-Programmable Gate Arrays) system is one of the most promising HPC platforms because FPGAs provide reconfigurability to accelerate different applications, faster processing, and more power-efficient and lower latency service. In these platforms, the CPU and the FPGA are tightly coupled with each other and share the same DRAM for better communication. The platform used in this work is the Intel© Xeon© Scalable Platform with Integrated FPGA (HARP2 Platform).The Decoupled Access/Execute framework is a new way of mapping algorithms efficiently on Reconfigurable platforms (DAER). This framework splits the application tasks into two parts, the data processing (Process Unit) and the data fetching (Fetch Unit). This division completely decouples access to memory by processing data, to achieve high performance by exploiting parallelism.This Diploma Thesis aims to implement the Jacobi algorithm with the DAER framework in the HARP platform for the solution of Laplace equations. The Jacobi method belongs to the Structured Grid algorithms that fall into the list of thirteen (13) Dwarfs that represent active areas in parallel computing. In this work, two architectures have been mapped to try to exploit the advantages of the DAER framework. The experiments were conducted in the Academic Compute Environment (ACE) that is located on the vLabs of Intel. The results of those experiments show that using the DAER framework in the Hybrid CPU-FPGA platform achieves up to 2x speed-up compared to the CPU-based solution.

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