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A Hardware - Accelerated cryptography IP for disaggregated datacenters

Drakoulaki Eleni

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URI: http://purl.tuc.gr/dl/dias/2E8922F9-4426-489C-A9F3-2AA8914B77F0
Year 2023
Type of Item Diploma Work
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Bibliographic Citation Eleni Drakoulaki, "A Hardware - Accelerated cryptography IP for disaggregated datacenters", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2023 https://doi.org/10.26233/heallink.tuc.96363
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Summary

The world generates an unfathomable amount of data every minute of every day, and it continues to multiply at a staggering rate. Organizations in every industry are rapidly moving from batch processing to real-time data streams to keep pace with modern demands. The need to secure and protect private and personal data is greater than ever, and the field of cryptography provides the tools to handle this task. This thesis presents a design for a hardware-accelerated cryptography IP with the goal to be incorporated into a disaggregated datacenter and protect the data without interfering with the bandwidth and latency requirements of the server. In this thesis, we present the implementation of the AES, RC6, and Blowfish algorithms, both encryption and decryption, in the Zynq UltraScale+ ZCU102 Evaluation Platform and their evaluation based on a series of simulation-level tests, with AES and RC6 achieving the best throughput at 12.79 Gbps, while AES kept the resource utilization at a low level. As well as, the evaluation of AES encryption and decryption design in a physical board, by using the PYNQ Z1 FPGA board, and its overall performance compared to a software implementation running in a high-speed server, and even though it loses in terms of performance against the Zynq UltraScale+ ZCU102, it proves that the design, while implemented at a small, low cost, low-power consumption FPGA board can perform as well in the case of encryption, or even two times better, in the case of decryption, against a high-speed server.

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