Institutional Repository
Technical University of Crete
Technical University of Crete
EN
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EL
| URI: | http://purl.tuc.gr/dl/dias/9505B547-AD0E-4FFF-B5E9-5C4E51327D13 | ||
| Year | 2023 | ||
| Type of Item | Diploma Work | ||
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| Bibliographic Citation | Evangelos Kioulos, "A Preliminary accuracy analysis of simulated RISC-V systems", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2023 https://doi.org/10.26233/heallink.tuc.98383 | ||
| Appears in Collections |
The RISC-V Instruction Set Architecture (ISA) maintains a surging interest both in industry and in academia due to its simplicity, extensibility, and open license. The integration of RISC-V ISA in the widely used gem5 simulator bridges the gap between RTL and ISA (Spike, QEMU) simulation, as it offers a micro-architectural simulator to the RISC-V ecosystem. This, however, raises uncertainty regarding the accuracy degree of the RISC-V related model implementations in gem5. Especially if we consider that they are still premature due to their recent adoption. The modelling accuracy is crucial as it is responsible for guiding properly research studies and pinpointing areas for optimization on various architectural design spaces. In this thesis, we aim to match the performance and energy costs of an ASIC RISC-V implementation, namely CVA6 (formerly known as Ariane), with a simulated RISC-V system in gem5. We present our experimental setup where we use the gem5 simulator to obtain the performance statistics and McPAT to estimate power and energy metrics. Afterwards, we proceed with an analysis plan to identify potential inaccuracies and flaws of the gem5 simulator. We then evaluate the performance of our simulated system using benchmarks from the RISC-V ecosystem and compare the results to published hardware implementations.
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