Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/0C23D37F-A312-4B1C-B8C5-6AF105C8A3F4 | ||
| Year | 2024 | ||
| Type of Item | Diploma Work | ||
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| Bibliographic Citation | Danai Metaxaki, "Design of a mm-wave low noise amplifier (LNA) in FDSOI CMOS technology", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2024 https://doi.org/10.26233/heallink.tuc.99231 | ||
| Appears in Collections |
In today’s data-driven world, where efficient data transmission is paramount, there’s an increasing adoption of 5G technology in both mobile and satellite communications. 5G offers a cost-effective, energy-efficient solution with broad global coverage. Operating in the Ka-band high-frequency spectrum, enables high-speed data transfer with minimal latency. Meeting these demands necessitates advancements in high-performance RF components. Low Noise Amplifiers (LNAs) serve as crucial components in the receiver chain, amplifying signals while minimizing added noise. Hence, designing high-performance LNAs that are cost-effective and offer integration advantages is essential to support technological advancements. This thesis focuses on designing a Low Noise Amplifier using 22nm FD-SOI technology. The design is based on a Single Stage Common Source Amplifier circuit with Inductive Degeneration, operating at a frequency of 28 GHz. Throughout the process, schematic design, optimization, layout design, and simulation are conducted to provide a comprehensive design approach. During the design process, Cadence’s Virtuoso software was utilized as the primary tool. The work resulted in notable outcomes, for a power consumption of 16.29 mW from a 0.8 V supply, the LNA achieves a NF of 1.88 dB, provides peak gain at 10.62 dB, area 0.15 mm2 and linearity of -3.6 dBm, reflecting the efficacy of the implemented design strategies. Τhe simplified EKV model and the design method based on inversion coefficient, were applied in this work to extract parameters and explore trade-offs, comparing them to the design measurements illustrating the efficacy of employing inversion coefficient in analog FD SOI circuit design.
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