Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
EN
|
EL
| URI | http://purl.tuc.gr/dl/dias/36252C00-F8C4-4D2A-95C3-FCDB1B23E697 | - |
| Αναγνωριστικό | https://doi.org/10.1109/FPL.2009.5272341 | - |
| Αναγνωριστικό | http://ieeexplore.ieee.org/document/5272341/ | - |
| Γλώσσα | en | - |
| Μέγεθος | 5 pages | en |
| Τίτλος | A reconfigurable architecture for the phylogenetic likelihood function | en |
| Δημιουργός | Alachiotis, Nikolaos | en |
| Δημιουργός | Stamatakis Alexandros | en |
| Δημιουργός | Σταματακης Αλεξανδρος | el |
| Δημιουργός | Sotiriadis Evripidis | en |
| Δημιουργός | Σωτηριαδης Ευριπιδης | el |
| Δημιουργός | Dollas Apostolos | en |
| Δημιουργός | Δολλας Αποστολος | el |
| Εκδότης | Institute of Electrical and Electronics Engineers | en |
| Περίληψη | As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run efficiently, as compared to a general-purpose computer. This paper presents an architecture that benefits from the large number of DSP modules in Xilinx technology to implement massive floating point arithmetic. Our architecture computes the Phylogenetic Likelihood Function (PLF) which accounts for approximately 95% of total execution time in all state-of-the-art Maximum Likelihood (ML) based programs for reconstruction of evolutionary relationships. We validate and assess performance of our architecture against a highly optimized and parallelized software implementation of the PLF that is based on RAxML, which is considered to be one of the fastest and most accurate programs for phylogenetic inference. Both software and hardware implementations use double precision floating point arithmetic. The new architecture achieves speedups ranging from 1.6 up to 7.2 compared to a high-end 8-way dual-core general-purpose computer running the aforementioned highly optimized OpenMP-based multi-threaded version of the PLF. | en |
| Τύπος | Δημοσίευση σε Συνέδριο | el |
| Τύπος | Conference Publication | en |
| Άδεια Χρήσης | http://creativecommons.org/licenses/by/4.0/ | en |
| Ημερομηνία | 2015-11-17 | - |
| Ημερομηνία Δημοσίευσης | 2009 | - |
| Θεματική Κατηγορία | Field programmable logic arrays | en |
| Θεματική Κατηγορία | FPGAs | en |
| Θεματική Κατηγορία | field programmable gate arrays | en |
| Θεματική Κατηγορία | field programmable logic arrays | en |
| Θεματική Κατηγορία | fpgas | en |
| Βιβλιογραφική Αναφορά | N. Alachiotis, A. Stamatakis, E. Sotiriades and A. Dollas, "A reconfigurable architecture for the phylogenetic likelihood function," in International Conference on Field Programmable Logic and Applications, 2009, pp. 674-678. doi: 10.1109/FPL.2009.5272341 | en |
Copyright © DIAS 2013
