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An FPGA-based sudoku solver based on simulated annealing methods

Malakonakis Pavlos, Smerdis Miltiadis, Sotiriadis Evripidis, Dollas Apostolos

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URIhttp://purl.tuc.gr/dl/dias/84EBD8AD-9090-4A3F-901E-6C4C5A6D7DBF-
Identifierhttps://doi.org/10.1109/FPT.2009.5377608-
Identifierhttp://ieeexplore.ieee.org/document/5377608/?reload=true&arnumber=5377608-
Languageen-
Extent4 pagesen
TitleAn FPGA-based sudoku solver based on simulated annealing methodsen
CreatorMalakonakis Pavlosen
CreatorΜαλακωνακης Παυλοςel
CreatorSmerdis Miltiadisen
CreatorΣμερδης Μιλτιαδηςel
CreatorSotiriadis Evripidisen
CreatorΣωτηριαδης Ευριπιδηςel
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryThe Sudoku simulated annealing solver -SSAS is a probabilistic Sudoku solver. The general design is capable of solving a Sudoku board of order up to fifteen (15 × 15 × 15 × 15). It has been designed and fully implemented on a Xilinx Virtex II Pro - based Digilent XUP board. The solver has a serial-port interface to download problems and upload results to a personal computer, according to the specifications of the relevant competition of the 2009 International Conference on Field Programmable Technology (FPT). The SSAS has solved in actual hardware Sudoku puzzles of up to order 12 within the competition-imposed time limits.en
Type of ItemΔημοσίευση σε Συνέδριοel
Type of ItemConference Publicationen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-17-
Date of Publication2009-
SubjectField programmable logic arraysen
SubjectFPGAsen
Subjectfield programmable gate arraysen
Subjectfield programmable logic arraysen
Subjectfpgasen
Bibliographic CitationP. Malakonakis, M. Smerdis, E. Sotiriades and A. Dollas, "An FPGA-based Sudoku Solver based on Simulated Annealing methods," in International Conference on Field-Programmable Technology, 2009, pp. 522-525. doi: 10.1109/FPT.2009.5377608en

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