Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI | http://purl.tuc.gr/dl/dias/AA74171F-9466-47DA-B700-F584A6974AB9 | - |
| Identifier | https://doi.org/10.1109/FPL.2008.4629900 | - |
| Identifier | http://ieeexplore.ieee.org/abstract/document/4629900/ | - |
| Language | en | - |
| Extent | 6 pages | en |
| Title | Modeling recursion data structures for FPGA-based implementation | en |
| Creator | Ninos Spyridon | en |
| Creator | Νινος Σπυριδων | el |
| Creator | Dollas Apostolos | en |
| Creator | Δολλας Αποστολος | el |
| Publisher | Institute of Electrical and Electronics Engineers | en |
| Content Summary | Recursion is a powerful technique used to solve problems with repeating patterns, and is a fundamental structure in software. To date there is no known general way to apply a recursive solution to reconfigurable hardware; it is considered difficult to implement, of low performance and resource-intensive. In this paper we extend previous results on hardware structures for recursion by V. Sklyarov, and we demonstrate that recursion can be efficiently implemented in a general way on FPGAs. We show that our general, non-optimized architecture presents approximately 3 times speedup against optimized software algorithm implementations. It also shows 75% speedup, at least 40% lower area utilization, and at the same time it is simpler, less designer time consuming and more general vs. previously published hardware implementations. | en |
| Type of Item | Δημοσίευση σε Συνέδριο | el |
| Type of Item | Conference Publication | en |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2015-11-17 | - |
| Date of Publication | 2008 | - |
| Subject | Field programmable logic arrays | en |
| Subject | FPGAs | en |
| Subject | field programmable gate arrays | en |
| Subject | field programmable logic arrays | en |
| Subject | fpgas | en |
| Bibliographic Citation | S. Ninos and A. Dollas, "Modeling recursion data structures for FPGA-based implementation," in International Conference on Field Programmable Logic and Applications, 2008, pp. 11-16. doi: 10.1109/FPL.2008.4629900 | en |
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