Institutional Repository
Technical University of Crete
Technical University of Crete
EN
|
EL
| URI | http://purl.tuc.gr/dl/dias/95931972-5301-4118-AD6D-D9AD1015F29C | - |
| Identifier | https://doi.org/10.26233/heallink.tuc.75213 | - |
| Language | en | - |
| Extent | 78 pages | en |
| Extent | 3,76 megabytes | en |
| Title | Implementation of an ARM processor with SIMD extensions using the Bluespec Hardware Description Language | en |
| Title | Υλοποίηση επεξεργαστή ARM με επέκταση εντολών SIMD με χρήση Γλώσσας Περιγραφής Υλικού Bluespec | el |
| Creator | Makrygiannis Konstantinos | en |
| Creator | Μακρυγιαννης Κωνσταντινος | el |
| Contributor [Thesis Supervisor] | Pnevmatikatos Dionysios | en |
| Contributor [Thesis Supervisor] | Πνευματικατος Διονυσιος | el |
| Contributor [Committee Member] | Dollas Apostolos | en |
| Contributor [Committee Member] | Δολλας Αποστολος | el |
| Contributor [Committee Member] | Theodoropoulos Dimitrios | en |
| Contributor [Committee Member] | Θεοδωροπουλος Δημητριος | el |
| Publisher | Πολυτεχνείο Κρήτης | el |
| Publisher | Technical University of Crete | en |
| Academic Unit | Technical University of Crete::School of Electrical and Computer Engineering | en |
| Academic Unit | Πολυτεχνείο Κρήτης::Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών | el |
| Content Summary | The goal of this thesis was to implement an ARM processor with Single Instruction Multiple Data (SIMD) extensions using the Bluespec System Verilog (BSV) as a Hardware Description Language (HDL). BSV has a fundamentally different approach to hardware design, comparing to other HDLs. It is based on circuit generation - rather than merely circuit description - and on atomic transactional rules instead of a globally synchronous view of the world. BSV language is considered a high-level functional HDL, which was essentially Haskell - extended to handle chip design and electronic design automation in general. BSV is partially evaluated (to convert the Haskell parts) and compiled to the Term Rewriting System (TRS). Our scalar processor supports a 3-stage pipeline (Fetch – Decode – Execute), belongs to the ARM7 family and uses a 32-bit architecture, which is based on ARMv4 instruction set. The SIMD unit works as an extension to the scalar part and is based on a modification of ARM NEON technology. The scalar part of the processor supports Data processing, Multiply, Long Multiply, Load/Store – Byte/Word and Branch instructions of the ARM Instruction Set Format, while the vector part supports Vector Data Processing, Vector Multiply and Vector Load/Store instructions. | en |
| Type of Item | Διπλωματική Εργασία | el |
| Type of Item | Diploma Work | en |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2018-05-17 | - |
| Date of Publication | 2018 | - |
| Subject | Bluespec | en |
| Subject | Vector processing | en |
| Subject | ARM | en |
| Bibliographic Citation | Konstantinos Makrygiannis, "Implementation of an ARM processor with SIMD extensions using the Bluespec Hardware Description Language", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2018 | en |
| Bibliographic Citation | Κωνσταντίνος Μακρυγιάννης, "Υλοποίηση επεξεργαστή ARM με επέκταση εντολών SIMD με χρήση Γλώσσας Περιγραφής Υλικού Bluespec ", Διπλωματική Εργασία, Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, Χανιά, Ελλάς, 2018 | el |
Copyright © DIAS 2013
