Institutional Repository
Technical University of Crete
Technical University of Crete
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EL
| URI: | http://purl.tuc.gr/dl/dias/AEED7410-A42D-41BF-A1EE-78D744786245 | ||
| Year | 2003 | ||
| Type of Item | Peer-Reviewed Journal Publication | ||
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| Bibliographic Citation | D. Pnevmatikatos, I. Sourdis , K. Vlachos,"An efficient and low-cost input/output subsystem for network processors .(2003).IEEE Design and Test of Computers [online]. pp. 56-64.Available:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.60.2374&rep=rep1&type=pdf | ||
| Appears in Collections |
We present the architecture and implementation of an input/output subsystem for a cost-effective network processor. We believe that adding processing power to a networking chip is relatively straightforward. However, transferring data to and from the processor(s) is insufficient for high wire speeds. To address this limitation we use a hardwired input/output subsystem transferring data directly into the processing core’s register file. Using a simple scalar RISC core at 200MHz, we are able to sustain state-full inspection firewall processing at 2.5Gbps TCP traffic.
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