Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/C0C396B2-1BA0-417F-BF5E-9BC2DD95B452 | ||
| Year | 2004 | ||
| Type of Item | Peer-Reviewed Journal Publication | ||
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| Bibliographic Citation | I. Papaefstathiou, S. Perissakis, T. Orphanoudakis, N. Nikolaou, G. Kornaros, D. Pnevmatikatos, G. Konstantoulakis, N. Zervos, "PR03: a hybrid NPU architecture," IEEE Micro, vol. 24, no. 5, pp. 20 - 33, March, 2004. doi: 10.1109/MM.2004.55 https://doi.org/10.1109/MM.2004.55 | ||
| Appears in Collections |
As the telecommunications industry recovers from the severe downturn of recent years, data traffic continues to exhibit a rate of increase that outpaces advances in VLSI technology. Therefore, lowering overall system cost at network processing nodes and maximizing network utilization - hence revenues - remain extremely important objectives. To address these issues, new semiconductor devices called network processing units (NPUs) have emerged. They are optimized to provide programmable processing of protocol data units (PDUs) in networks with diverse requirements while efficiently supporting current and emerging protocols and services. NPUs promise to deliver an ASICs speed with a CPU's programmability, thus augmenting the capacity and features of network nodes that forward and manipulate data traffic. The Programmable Protocol Processor (PRO3) system reduces the overhead incurred by common "BRUTE-FORCE" architectures by using the least-required hardware resources for certain common well-defined tasks.
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