Institutional Repository
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/08D76F80-8D25-43A2-9BA5-0199300A8623 | ||
| Year | 2016 | ||
| Type of Item | Peer-Reviewed Journal Publication | ||
| License |
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| Bibliographic Citation | G. Charitopoulos, D. Pnevmatikatos, M. D. Santambrogio, K. Papadimitriou and D. Pau, "A run-time system for partially reconfigurable FPGAs: the case of STMicroelectronics SPEAr board," Adv. Par. Com., vol. 27, pp. 553-562, 2016. doi: 10.3233/978-1-61499-621-7-553 https://doi.org/10.3233/978-1-61499-621-7-553 | ||
| Appears in Collections |
During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM processor alongside with a Virtex-5 FPGA daughter-board. While partial reconfiguration in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The paper discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogurable) hardware and software tasks.We also propose improvements that can be exploited in order to make the PR utility more easy-to-use on future projects on the SPEAr platform.
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