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Compact modeling of SIC and gan junction FETS at high temperature

Makris Nikolaos, Zekentes, Konstantinos, Bucher Matthias

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URI: http://purl.tuc.gr/dl/dias/F5C955D4-9356-4680-A972-99DE10D0ECC9
Year 2019
Type of Item Peer-Reviewed Journal Publication
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Bibliographic Citation N. Makris, K. Zekentes and M. Bucher, “Compact modeling of SiC and GaN junction FETs at high temperature,” Mater. Sci. Forum, vol. 963, pp. 683–687, Jul. 2019. https://doi.org/10.4028/www.scientific.net/msf.963.683 https://doi.org/10.4028/www.scientific.net/MSF.963.683
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Summary

High temperatures and other harsh environments are domains of predilection for Junction FETs, particularly when wide band-gap semiconductors such as SiC or GaN are used. The present work describes the new compact model of double-gate (DG) JFETs which is compared to TCAD simulations of SiC and GaN JFETs over a wide temperature range up to 500ºC. The compact model is shown to be predictive of device behavior, for static (current-voltage) as well as dynamic (capacitance-voltage) behavior of long-channel DG JFETs.

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