Journal Publications

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	361-375 out of 758 results
361	E. Koutroulis, K. Kalaitzakis and A. Dollas, "High frequency pulse width modulation implementation using FPGA and CPLD ICs," J. Syst. Architect., vol. 52, no. 6, pp. 332-344, Jun. 2006. doi: 10.1016/j.sysarc.2005.09.001	2015-11-17
362	A. Deligiannakis, Y. Kotidis, V. Stoumpos and A. Delis, "Collection trees for event-monitoring queries", Inform. Syst., vol. 36, no. 2, pp. 386-405, Apr. 2011. doi:10.1016/j.is.2010.08.003	2015-11-17
363	I. Smonou, S. Khan, C. S. Foote, Y. Elemes, I. Mavridis, A. Pantidou, and M. Orfanopoulos, "Reactions of Phenyltriazolinedione with Alkenes. Stereochemistry and Methanol Adducts to Aziridinium Imide Intermediates", Journal of the American Chemical Society, vol. 117, no. 7081, 1995.	2015-11-16
364	P. Mattheakis, I. Papaefstathiou, "Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems," ACM Transactions on Architecture and Code Optimization, vol. 9, no. 4., Jan., 2013. doi: 10.1145/2400682.2400710	2015-11-16
365	I. Mavroidis, D. Mavroidis, I. Papaefstathiou, "Accelerating Emulation and Providing Full Chip Observability and Controllability," IEEE Design and Test, vol. 26, no. 6, pp. 84-94, Nov./Dec. 2009. doi: 10.1109/MDT.2009.136	2015-11-16
366	D. Simos, I. Papaefstathiou, M. Katevenis, "Towards Fabric-On-a-chip(FoC) : A 400Gbps 32×32 Variable-Packet-Size Buffered Crossbar (CICQ) Single-Chip Switch Core," IEEE Design and Test, to be published.	2015-11-16
367	I. Papaefstathiou, C. Manifavas. (2014). Evaluation of Micropayment Transaction Cost. Journal of Electronic Commerce Research.[Online]. Available: http://web.csulb.edu/journals/jecr/issues/20042/Paper3.pdf	2015-11-16
368	I. Papaefstathiou, A. Nikologiannis, B. Doshi, E. Grosse. (2004,Sept/Oct). Network Processors for Future High-End Systems and Applications. IEEE Micro. [Online]. Available: https://www.computer.org/csdl/mags/mi/2004/05/m5007.pdf	2015-11-16
369	I. Papaefstathiou, S. Perissakis, T. Orphanoudakis, N. Nikolaou, G. Kornaros, D. Pnevmatikatos, G. Konstantoulakis, N. Zervos, "PR03: a hybrid NPU architecture," IEEE Micro, vol. 24, no. 5, pp. 20 - 33, March, 2004. doi: 10.1109/MM.2004.55	2015-11-16
370	I. Papaefstathiou, K. Vlachos, V. Nikolaou, W. Lawrence, " Packet processing acceleration with a 3-stage re-configurable pipeline engine," IEEE Communications Letters, vol. 8, no. 3, Mar., 2004.	2015-11-16
371	I. Papaefstathiou, " Low-level Hardware Compression for Multi-Gigabit Networks," Journal of Circuits, Systems and Computers, vol. 13, no. 6, pp. 1307-1319, Dec. 2004. doi: 10.1142/S0218126604001969	2015-11-16
372	I. Papaefstathiou, "Titan II: an IPComp processor for 10Gbit/sec networks," IEEE Design and Test (DandT)., pp. 234 - 235, Nov. 2004. doi:10.1109/ISVLSI.2003.1183479	2015-11-16
373	I. Papaefstathiou, V. Papaefstathiou, C. Sotiriou, "Elsevier Journal on Microprocessors and Microsystems," vol. 28, no. 10, pp. 561-571, Sept. 2013. doi:10.1016/j.micpro.2004.08.009	2015-11-16
374	M. Christoulakis, A. Pitsiladis, P. Stergiopoulos, N. Moumoutzis, A. Moraiti, I. Maragoudakis and S. Christodoulakis, "Creative collaborative experiences with interactive shadow theater", Formazione & Insegnamento XII, vol. 2, 2014.	2015-11-15
375	D. Dochev, R. Pavlov, O. Hutter, I. Simonics and P. Arapi, "Virtual campuses - architectures and design solutions", Cybern. and Inform. Techn., vol. 4. no. 1, pp. 54-64, 2004.	2015-11-15
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