Ιδρυματικό Αποθετήριο
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
EN
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| URI: | http://purl.tuc.gr/dl/dias/21CFE9E6-9F47-47F9-8686-12F0E4738802 | ||
| Έτος | 2004 | ||
| Τύπος | Δημοσίευση σε Περιοδικό χωρίς Κριτές | ||
| Άδεια Χρήσης |
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| Βιβλιογραφική Αναφορά | I. Papaefstathiou, "Titan II: an IPComp processor for 10Gbit/sec networks," IEEE Design and Test (DandT)., pp. 234 - 235, Nov. 2004. doi:10.1109/ISVLSI.2003.1183479 https://doi.org/10.1109/MDT.2004.100 | ||
| Εμφανίζεται στις Συλλογές |
As it has already been proved, link layer compression is very effective when used in packet networks. In particular, IP payload compression is especially useful when encryption is applied to the network packets. Encrypting the IP packets causes the data to be random in nature, rendering compression at lower protocol layers. As a result, and since it is believed encryption will be applied to the vast majority of IP networks in the near future, we claim that an IP packet compressor will be required for taking full advantage of the capabilities of the future networks. However one of the major problems with such network compression schemes, is that there should exist hardware modules capable of compressing the network streams up to the speed of the state-of-the-art links. In this paper we present such a hardware compressor/decompressor core that can work at speeds up to 10Gb/sec it is fairly inexpensive and can very easily be plugged into an existing network node without causing any side effects. The presented design can be easily incorporated in a network System-on-a-Chip (Soc).
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