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Explicit communication and synchronization in SARC

Pnevmatikatos Dionysios, Katevenis, Manolis G, Vassilis Papaefstathiou, Stamatis G. Kavadias

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URI: http://purl.tuc.gr/dl/dias/93B17D95-5562-47F0-8ABD-7ED0146FC7F1
Year 2010
Type of Item Peer-Reviewed Journal Publication
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Bibliographic Citation M. Katevenis, V. Papaefstathiou, S. G. Kavadias, D. N. Pnevmatikatos, F. Silla, D. S. Nikolopoulos, "Explicit ommunication and synchronization in SARC’’. IEEE Micro, vol. 30, no. 5, pp. 30-41, 2010.10.1109/MM.2010.77 https://doi.org/10.1109/MM.2010.77
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Summary

A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency

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